Name: ST STM32F103RCT6
Brand: ST
Availability: InStock

产品实拍图

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产品应用与封装尺寸

图纸取自原厂规格书，点击可放大查看原始尺寸标注。

引脚定义与内部结构

引脚	符号	名称
73	NC
72	PA 13
71	PA 12
70	PA 11
69	PA 10
68	PA 9
67	PA 8
1	I = input, O = output, S = supply.
3	Function availability depends on the chosen device.

数据来源：原厂规格书引脚图

关键参数速览

工作温度 TA: T a ble 7. Voltage

产品特点 Features

Core: ARM 32-bit Cortex™-M3 CPU
72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
Single-cycle multiplication and hardware division
Memories
256 to 512 Kbytes of Flash memory up to 64 Kbytes of SRAM
Flexible static memory controller with 4
Chip Select. Supports Compact Flash,
SRAM, PSRAM, NOR and NAND memories
LCD parallel interface, 8080/6800 modes
Clock, reset and supply management
2.0 to 3.6 V application supply and I/Os
POR, PDR, and programmable voltage detector (PVD)
4-to-16 MHz crystal oscillator
Internal 8 MHz factory-trimmed RC
Internal 40 kHz RC with calibration

绝对最大额定值 Absolute Maximum Ratings（TA = 25°C）

超过下表数值可能造成器件永久损坏，设计时请留余量。

符号	额定值	最小	最大
at these conditions is	not implied. Exposure to	maximum rating conditions	for extended
T a ble 7. Voltage	characteristics
External	main supply voltage (including	V
V –V		DDA –0.3	4.0
Input	voltage on five volt tolerant pin	V − 0.3	V + 4.0
Input	voltage on any other pin	V − 0.3	4.0
\|ΔV \| Variations	between different V power	pins	50
		see Section	5.3.12:

数据来源：原厂规格书

电气特性 Electrical Characteristics（TA = 25°C）

5.1	参数	条件
	Unless otherwise	specified, all voltages are referenced to V .
	the selected	temperature range).
	Typical ADC	accuracy values are determined by characterization of a batch of samples from
●	All I/O pins are in input mode with a static value at V	or V (no load).
72 MHz	51	30.5
48 MHz	34.6	20.7
36 MHz	26.6	16.2
24 MHz	18.5	11.4
16 MHz	12.8	8.2
4 MHz	4.2	3.1
2 MHz	2.7	2.1
1 MHz	2	1.7
500 kHz	1.6	1.4
125 kHz	1.3	1.2
64 MHz	45	27
48 MHz	34	20.1
36 MHz	26	15.6
24 MHz	17.9	10.8
2 MHz	2.1	1.5
1 MHz	1.4	1.1
500 kHz	1	0.8
125 kHz	0.7	0.6
T able 28. PLL	characteristics
PLL	input clock(2) 1	8.0 25 MHz
PLL	input clock duty cycle 40	60 %
f PLL	multiplier output clock 16	72 MHz
t PLL	lock time	200 µs
Jitter	Cycle-to-cycle jitter	300 ps
The characteristics	are given at T = –40 to 105 °C unless	otherwise specified.
T able 29. Flash	memory characteristics
t 16-bit	programming time T = –40 to +105 °C	40 52.5 70 µs
t Page (2	KB) erase time T = –40 to +105 °C	20 40 ms
t Mass erase	time T = –40 to +105 °C	20 40 ms
	f = 72 MHz with 2 wait	28 mA
	states, V = 3.3 V	7 mA
	f = 72 MHz, V = 3.3	V
I Supply	current HCLK DD	5 mA
	f = 72 MHz, V = 3.3	V 50 µA
	V = 3.0 to 3.6 V
V Programming	voltage	2 3.6 V
t	t	t
v(NWE_NE)	w(NWE)	h(NE_NWE)
t	t	t
v(A_NE)	v(Data_NADV)	h(Data_NWE)
FSMC_AD[15:0]	Address	Data
w(NE)	HCLK	HCLK
v(NWE_NE)	HCLK	HCLK
w(NWE)	HCLK	HCLK
w(NADV)	HCLK	HCLK

特性曲线（Typical Performance Curves）

订货信息与供货形式

This	datasheet	provides	the	ordering	information	and	mechanical	器件	特性
the	STM32F103xC,		STM32F103xD		and	STM32F103xE	high-density		performance line
please	refer to	Section	2.2:	Full	compatibility	throughout	the family.
The	high-density		STM32F103xx	datasheet	should	be	read in	conjunction	with the
For	information	on	programming,	erasing	and	protection	of the	internal Flash	memory
please	refer to	the	STM32F10xxx	Flash	programming		manual.
The	reference	and Flash		programming	manuals	are both	available	from the
For	information	on the	Cortex™-M3		core please	refer to	the	Cortex™-M3	Technical

应用领域 Applications

Closely coupled NVIC core interfaceAllows early processing of interruptsSupport for tail-chainingProcessor state automatically saved2.3.9 Clocks and startupExample 1: High-performance application

资料下载

📄 STM32F103RCT6 规格书 PDF

规格书为原厂公开资料，点击在新窗口打开下载。

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STM32F103RCT6 存储芯片