产品应用与封装尺寸
图纸取自原厂规格书，点击可放大查看原始尺寸标注。
引脚定义与内部结构
| 引脚 | 符号 | 名称 |
|---|---|---|
| 1 | V | |
| 2 | V | |
| 3 | V | |
| 5 | V | |
| 6 | MDAT | |
| 7 | MCLK | |
| 8 | V |
数据来源：原厂规格书引脚图
关键参数速览
- 隔离电压 VISO
- 1 kV; See Definitions
- 电源电压 VCC
- 6.0
- 工作温度 TA
- +105
产品特点 Features
- modes (combinations of speed and resolution), three different pre-trigger modes (allows conversion time <
- Digital Current Sensing Circuit
- Serial Configuration port. A second multiplexed input is available to allow measurements with a second isolated modulator without additional hardware. Refer to the
- HCPL-0872 data sheet for details.
- Notes:
- SPI and QSPI are trademarks of Motorola Corp.
- FLOATING
- POSITIVE SUPPLY
- GATE R1
- DRIVE
- CIRCUIT
- D1 C1a C1b
- 5.1 V 1 µF 0.1 µF
- R2a 22 Ω
- MOTOR C2 10
- + – R2b 22 Ω
绝对最大额定值 Absolute Maximum Ratings（TA = 25°C）
超过下表数值可能造成器件永久损坏，设计时请留余量。
| 参数 | 符号 | 最小 | 最大 | 单位 |
|---|---|---|---|---|
| Storage Temperature | T | -55 | +125 | °C |
| Ambient Operating Temperature | T | -40 | +105 | °C |
| Supply Voltage | V , V DD1 DD2 | -0.5 | 6.0 | V |
| Steady-State Input Voltage[1,3] | V +, V – IN IN | -2 | V + 0.5 DD1 | V |
| Two-Second Transient Input | Voltage[2] V +, V – IN IN | -6 | V + 0.5 DD1 | V |
| Digital Output Voltages | MCLK, MDAT | -0.5 | V +0.5 DD2 | V |
| Lead Solder Temperature | 260°C for 10 | sec., 1.6 mm below | seating plane |
数据来源：原厂规格书
安全与绝缘额定值（DIN EN/IEC 60747−5−5）
| 说明 | 符号 | 值 | 单位 |
|---|---|---|---|
| Installation classification per DIN VDE 0110/1.89, | Table 1 | ||
| for rated mains voltage ≤ 150 V rms | I – IV | ||
| for rated mains voltage ≤ 300 V rms | I – IV | ||
| for rated mains voltage ≤ 450 V rms | I – IV | ||
| for rated mains voltage ≤ 600 V rms | I – IV | ||
| for rated mains voltage ≤ 1000 V rms | I – III | ||
| Pollution Degree (DIN VDE 0110/1.89) | 2 | ||
| Input to Output Test Voltage, Method b | V | 2652 | Vpeak |
| V x 1.875=V , 100% Production Test with t | =1 sec, Partial discharge < 5 pC | ||
| Input to Output Test Voltage, Method a | V | 2262 | Vpeak |
| V x 1.6=V , Type and Sample Test, t =10 | sec, Partial discharge < 5 pC | ||
| Highest Allowable Overvoltage (Transient | Overvoltage t = 60 sec) V | 8000 | Vpeak |
| Minimum External Air Gap L(101) | 8.0 mm Measured from input terminals | to output | terminals, |
| (Clearance) | shortest distance through | air. | |
| (Creepage) | shortest distance path along | body. | |
| Minimum Internal Plastic Gap | 0.5 mm Through insulation distance, | conductor to | conductor, |
| (Internal Clearance) | usually the direct distance | between the | photoemitter and |
| photodetector inside the | optocoupler cavity | ||
| Tracking Resistance CTI | > 175 V DIN IEC 112/VDE 0303 Part | 1 | |
| Isolation Group | IIIa Material Group (DIN VDE | 0110, 1/89, Table | 1) |
电气特性 Electrical Characteristics（TA = 25°C）
| 参数 | 符号 | 最小 | Typ.[1] | 最大 | 单位 | 测试条件 | 图号 |
|---|---|---|---|---|---|---|---|
| A | DD1 | DD2 | IN | ||||
| V – = 0 V (single-ended | connection); | tested with | Sinc3 filter, | 256 | decimation | ratio. | |
| Resolution | 16 | Bits | Decimation filter output 16 bits | set to | |||
| Integral Nonlinearity | INL | -15 | 3 | 15 | LSB | T = –40°C to +85°C; | |
| see Definitions section | |||||||
| -25 | 3 | 25 | LSB | T = 85°C to 105°C | |||
| Differential Nonlinearity | DNL | -0.9 | 0.9 | LSB | No missing codes, guaranteed | by | |
| design; see Definitions | section | ||||||
| Offset Error | V | -1 | 0.3 | 2 | mV | T = –40°C to +105°C; | 5 |
| see Definitions section | |||||||
| Offset Drift vs. Temperature | TCV OS | 1.0 | 3.5 | µV/°C | V = 5 V DD1 | ||
| Offset Drift vs. V | 200 | µV/V | |||||
| Internal Reference | Voltage V | 320 | mV | ||||
| Reference Voltage | Tolerance G E | -1 | 1 | % | T = 25°C, V + = –320 to A IN | +320 mV; | |
| see Definitions section | |||||||
| -2 | 2 | % | T = –40°C to +105°C, | 6 | |||
| V + = –320 to +320 mV | |||||||
| V Drift vs. Temperature | TCG | 60 | ppm/°C | ||||
| V Drift vs. V | -1.3 | mV/V | Note 4 | ||||
| Full-Scale Differential | Voltage FSR | ±320 | mV | V = V + – V –; Note 2 | |||
| Average Input Bias | Current I | -0.3 | µA | V = 5V, V = 5V, V + | = 0 V; 7 | ||
| INA | DD1 DD2 IN | ||||||
| Average Input Resistance | R | 24 | kW | Across V + or V – to GND1; | |||
| Input Capacitance | C | 8 | pF | Across V + or V – to GND1 | |||
| DYNAMIC CHARACTERISTICS | V + = 400 mVpp, 1 kHz | sine wave | |||||
| Signal-to-Noise Ratio | SNR | 68 | 78 | dB | T = –40°C to +105°C; | 8 | |
| see Definitions section | |||||||
| Signal-to-(Noise + | Distortion) SNDR | 65 | 75 | dB | T = –40°C to +105°C; | 9 | |
| Ratio | see Definitions section | ||||||
| Effective Number of | Bits ENOB | 12 | Bits | see Definitions section | |||
| Isolation Transient | Immunity CMR | 25 | kV/µV | V = 1 kV; See Definitions | section | ||
| Common-Mode Rejection | Ratio CMRR | 74 | dB | ||||
| Output High Voltage | V | V – | V – | V | I = –200 µA | ||
| OH | DD2 | DD2 | OUT | ||||
| Output Low Voltage | V | 0.6 | V | I = +1.6 mA | |||
| V Supply Current | I | 9 | 14 | mA | V + = –320 mV to +320 | mV 10 | |
| DD1 | DD1 | IN | |||||
| V Supply Current | I | 5.2 | 8 | mA | V = 5 V supply | 11 | |
| DD2 | DD2 | DD2 | |||||
| 4.6 | 7 | mA | V = 3.3 V supply DD2 | 12 | |||
| 4. VREF Drift vs. VDD1 can | be expressed as –0.4%/V | with reference | to VREF. | ||||
| Unless otherwise noted, | T = -40°C to +105°C, V | = 4.5 | V to 5.5 | V, V | = 3 V | to 5.5 V. | |
| Modulator Clock Output | Frequency f | 9 | 10 | 11 | MHz | Clock duty cycle 40% to | 60% 13 |
| Data Access Time After | MCLK Rising Edge t | 40 | ns | C = 15 pF | 4 | ||
| Data Hold Time After MCLK | Rising Edge t | 10 | ns | C = 15 pF | 4 | ||
| Input-Output Momentary | V | 5000 | Vrms | RH < 50%, t = 1 min, | 1, 2 |
特性曲线（Typical Performance Curves）
相关 / 可替代型号
以上型号来自规格书与型号命名比对，参数需以各自规格书为准；下单前请与销售确认封装与脚位。